1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to the selective formation of dielectric layer for a semiconductor device.
2. Discussion of Related Art
One of the common techniques of forming a dielectric layer on a semiconductor device is deposition followed by etching. The dielectric layer is first blanket deposited onto a semiconductor film. Next, a photo-resist film is deposited on the dielectric layer. The photo-resist film is then masked, exposed and developed into a desired pattern that exposes certain portions of the dielectric layer for patterning. Etching is then performed to remove portions of the dielectric layer not covered by the patterned photo-resist film, thus forming a patterned dielectric layer. However, etching may cause damage to the underlying semiconductor film, which affects the performance of the semiconductor device.
Furthermore, in trying to improve the performance of semiconductor devices, new materials have been proposed for use. One example is the substitution of silicon materials used in transistors with III-V compound semiconductor materials that consist of elements from columns III and V of the periodic table. Examples of III-V compound semiconductors are indium antimonide (InSb) and gallium arsenide (GaAs).
Replacing silicon in the transistor channel with III-V compound semiconductor materials results in much higher electron mobility in the transistor channel, which leads to higher performance and less energy consumption. One type of transistor that utilizes III-V compound semiconductor materials is the III-V quantum well transistor. III-V quantum well transistors have shown to be suitable for high speed and low power logic applications. In comparison with metal oxide semiconductor field effect transistors (MOSFETS), quantum well transistors have shown to provide faster switching speed while reducing power consumption.
An example of a conventional III-V quantum well transistor is illustrated in FIG. 1. III-V quantum well transistor 100 includes a semi-insulating gallium arsenide (GaAs) substrate 110, a semiconductor epitaxial structure 120, a Schottky metal gate 160 and ohmic contacts 161, 162. The semiconductor epitaxial structure 120 consists of an aluminum indium antimony (AlInSb) buffer layer 122, a channel layer 124 and an AlInSb barrier layer 126. Channel layer 124 can be made of indium antimony (InSb) and is formed between barrier layer 126 and buffer layer 122. The Schottky metal gate 160 is formed on a recess 146 etched on the top of the AlInSb barrier layer 126. Ohmic contacts 161, 162 can be source and drain contacts.
As illustrated in FIG. 1, III-V quantum well transistors currently rely on Schottky barrier height as the junction barrier between the channel and gate. As a result, the on-to-off current ratio for these III-V quantum well transistors does not meet high-speed requirements for advance logic applications. Furthermore, the quiescent-state leakage currents present in Schottky metal gates affect the integration of III-V quantum well transistors into large-scale integrated circuits.
Hence, there is need for an improved method of fabricating a semiconductor device that overcomes the limitations of Schottky metal gates as well as minimizing damages associated with etching.